Top 17 VLSI Interview Questions & Answers 10) Explain why present VLSI circuits use MOSFETs instead of BJTs? Download PDF. VLSI CMOS interview questions and answers - Free download as Word Doc . doc), PDF File .pdf), Text File .txt) or read online for free. VLSI interview questions with answers - Ebook _ VLSI Design Interview Questions With Answers - aracer.mobi - Download as PDF File .pdf), Text File .txt) or.
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+ Vlsi Interview Questions and Answers, Question1: Why does the present VLSI circuits use MOSFETs instead of BJTs? Question2: What are the various. This post is mainly for those who are going to face interviews(mainly vlsi). when i tried to search for interview questions in the forum there was. View aracer.mobi from EE L at University of Southern California. http:/aracer.mobi 1.
Clock skew can be minimized by proper routing of clock signal clock distribution tree or putting variable delay buffer so that all clock inputs arrive at the same time 3 What is slack? The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'..
Negative slack implies that the 'actually happen' time is later than the 'deadline' time. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. The following figure shows a synchronous alternative to the gated clock using a data path. When the enable is High. When the enable is Low. For a latch. FF on the other hand. Tie one of xor gates input to 0 it will act as buffer. Tie one of xor gates input to 1 it will act as inverter.
They both require the use of clock signal and are used in sequential logic. The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. Difference between heap and stack?
The Stack is more or less responsible for keeping track of what's executing in our code or what's been "called". A Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions. The Heap is more or less responsible for keeping track of our objects our data.
The Heap is similar except that its purpose is to hold information not keep track of execution most of the time so anything in our Heap can be accessed at any time.
The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet.. When we're done with the top box the method is done executing we throw it away and proceed to use the stuff in the previous box on the top of the stack. With the Heap. Think of the Stack as a series of boxes stacked one on top of the next..
We can only use what's in the top box on the stack. We keep track of what's going on in our application by stacking another box on top every time we call a method called a Frame. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it. A state machine which uses only Input Actions. The outputs are held until you go to some other state Mealy machine: Mealy machines give you outputs instantly. A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine.
Moore overcomes glitches as output dependent on only states and not the input signal level. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM. All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine.
For a state machine with 9. The models selected will influence a design but there are no general indications as to which model is better.. Moore machine: Choice of a model depends on the application.
Common classifications used to describe the state encoding of an FSM are Binary or highly encoded and One hot. A onehot FSM design requires a flip-flop for each state in the design and only one flip- flop the flip-flop representing the current or "hot" state is set at a time in a one hot FSM design.
Adv and Disadv In Mealy as the output variable is a function both input and state. FSM2 Receiver generally a slow module asserts the ack acknowledge signal. The following section explains clock domain interfacing One of the biggest challenges of system-on-chip SOC designs is that different blocks operate on independent clocks.
To avoid this we go for double or triple stage synchronizers. The figure below shows how this is done. Clock Domain Crossing. Integrating these blocks via the processor bus. FSM1 Transmitter asserts the req request signal. You can find answer to this in timing. It uses a multiplex scheme to save input pins. SDRAM receives its address command in two address words. This is the basic question that many interviewers ask. It is well known that in left shift all bits will be shifted left and LSB will be appended with 0 and in right shift all bits will be shifted right and MSB will be appended with 0 this is a straightforward answer What is expected is in a left shift value gets Multiplied by 2 eg: Synchronous reset logic will synthesize to smaller flip-flops.
In some designs. This answers why most signals are active low. Disadvantages of asynchronous reset: Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock[ if you have a gated clock to save power. Asynchronous reset: The biggest problem with asynchronous resets is the reset release. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.
The clock works as a filter for small reset glitches. Using an asynchronous reset. Disadvantages of synchronous reset: Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset signal from any other data signal. Designs that are pushing the limit for data path timing.. Only an asynchronous reset will work in this situation. But in such a case. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present.
If you consider the transistor level of a module. Setup time signifies maximum delay constraints. How can you rectify it? The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0. By connecting the J input to the K through the inverter. D-latch is level sensitive where as flip-flop is edge sensitive. Setup time is critical for establishing the maximum clock frequency.
Hence the S and R inputs will act as J and K respectively. To avoid this undesirable operation. What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? Is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line.
By giving the feed back we can convert. Flip-flops are made up of latches. XOR each bits of A with B for e.. XNOR using 2: Using 2: Freq of operation: This could also be called as odd parity generator since with this additional 1 as output the total number of 1's will be ODD..
A xor B and so on. Design all the basic gates NOT. Nth XNOR gates output is final output. After how many clock cycles will it return to the initial state?
How does this circuit work? Explain in detail? The line should keep moving unless any of the following conditions arise: Then the full adder works like a full subtractor 39 A very good interview question.. It should not use any multiplier circuits.
See how 1. What is difference between setup and hold time. Other input to the xor being one. Wouldn't this be a possible solution to your question since it only will use a counter.
But for hold time. How many minimum number of 2 input NAND gates are required? To get the next square. The hint is hold time doesn't depend on clock..
The input carry bit to the full adder should be made It should use Multiplexers and other logic? This is interesting. The interviewer was looking for one specific reason. Setup violations are related to two edges of clock. It seems it would take n clock cycles to calculate square of n. Then the memory device goes to the appropriate address and outputs the associate data.
The device contains an encryption code. This path can never be activated since if the A input of the first MUX is activated. This creates a read access from the memory. The output encrypted data should be at the same rate as the input data but no necessarily with the same phase. LFSR is a linear feedback shift register where the input bit is driven by a linear function of the overall shift register value.
A synchronized clock is provided to this system as well. List a few of its industry applications. By timing all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit. Removal of false paths makes circuit testable and its timing performance predictable sometimes faster.
FLASH and etc. An example of a false path is shown in figure below. This memory functionality can be achieved by using a PROM. In encryption operation.. This is because it is likely that low-skew processor has better designed clock tree with more powerful and number of buffers and overheads to make skew better.
Which one is likely to have more power? Clock skew of 50ps is more likely to have clock power. Place and Route tools are capable of fixing multi-cycle paths problem. Which circuit has a less propagation delay? The synchronous counter will have lesser delay as the input to each flop is readily available before the clock edge.
Whereas the cascade counter will take long time as the. First circuit is synchronous and second is "ripple" cascading. Multi-cycle paths are paths between registers that take more than one clock cycle to become stable. For ex. This means that the combinatorial block the Unrolled Cordic can take up to 4 clock periods 25MHz to propagate its result.
So the delay will be propagating.
FIFO does not have address lines Ram is used for storage purpose where as fifo is used for synchronization purpose i. Use minimum hardware to build a circuit to indicate the direction of rotating. They are placed like at the drawing. If the circle rotates the way clock sensor sees the light first while D input second sensor is zero.
For Eg: One of them is connected to the data input of D flip-flop. I guess this is the minimum number of gates that need to be used.
Same as above except the inputs for the second XNOR gate. Explain your answer? What is the max clock frequency of the circuit. Even though there are clock layout strategies H-tree that can in theory reduce clock skew to zero by having the same path length from each flip-flop from the pll. To avoid this we need to use even number of inverters buffers. Here we need to use 2 inverters each with a delay of 1ns.
And there is a hold time violation in the circuit. What is the Maximum Frequency of Operation? Are there any hold time violations for FF2? If yes. With these microprocessors. A caching method in which modifications to data in the cache aren't copied to the cache source until absolutely necessary. It is always n-1 Where n is number of inputs.
With this performance improvement comes a slight risk that data may be lost if the system crashes. So 16 input parity generator will require 15 two input xor's. The receiver must decide the clocking of the signal on it's own. Here we can use the 2's compliment method addition. Write-back caching yields somewhat better performance than write-through caching because it reduces the number of write operations to main memory. Asynchronous systems do not send separate information to indicate the encoding or clocking information.
This information is not in the data in the signal sent from transmitting unit. Write-back caching is available on many microprocessors.
In contrast. So using a 4 bit binary adder we can just subract the given binary no from i. This means that the receiver must decide where to look in the signal stream to find ones and zeroes. A write-back cache is also called a copy-back cache. Synchronous systems negotiate the connection at the data-link level before communication begins.
For example. More advanced systems may negotiate things like error correction and compression. Multimedia stream require an isochronous transport mechanism to ensure that data is delivered as fast as it is displayed and to ensure that the audio is synchronized with the video.
Basic synchronous systems will synchronize two clocks before transmission. VLSI is a level of complexity and integration in a chip that demands Electronic Design Automation tools in order to succeed. There are no precise definitions. Was it gates? My professor simply told me that. SoC is that level of integration onto a chip that demands more expertise beyond traditional skills of electronics. Repeated Shift and Add Repeated shift and add. Here is my sense of it all.
Maybe more pragmatically. I think that. In other words. Shifting each position left is equivalent to multiplying by 2. If you know what JTAG boundary scan is. ASIC designer may.. Scan does not help you test whether your Design functions as intended. Synthesis and a library of primitive cells e.
All these things can be intermixed in hybrid sorts of ways.
Full Custom. Higher human crafting and less reliance on standard cells takes more time and implies higher NRE costs. A bit pattern almost like a software program is loaded into the already manufactured device which essentially interconnects lots of available gates to meet the designers purposes. Scan tests for defects in the chip's circuitry after it is manufactured e. ASIC designers usually implement the scan themselves and occurs just after synthesis.
PAD cells that are wired together real libraries are not this simple. Design usually is NOT done at a transistor level. DRAM memory. Property blocks on it and is thus highly centered with issues like Reuse. FPGAs are now available that have microprocessor embedded within them which were designed in a full custom manner. A chip designed for a specific application. Automated tools are certainly used to wire up different parts of the circuit and maybe even manipulate repeat.
Vectors" that the Scan circuitry enables to be introduced into the chip. VBS changes the width of the depletion layer and therefore also the voltage across the oxide due to the change of the charge in the depletion region. These bit vectors are shifted into the chip on the scan chains.
ASIC designers do not have this luxury and must handle all the manufacturing test details themselves. Scan testing typically does not test memories no flip-flops!
This results in a difference in threshold voltage which equals the difference in charge in the depletion region divided by the oxide capacitance. Here's a brief summary: If any vectors do not match. The voltage difference between the source and the bulk. Fabs normally supply antenna rules.
LVS tends to consider transistor fingers to be the same as an extra-wide transistor. LVS is a process that confirms that the layout has the same structure as the associated schematic. DRC exhaustively compares the physical netlist against a set of "foundry design rules" from the foundry operator. The word antenna is somewhat of a misnomer in this context—the problem is really the collection of charge. If they are the same. It then generates a netlist from each one and compares them.
Functionality of. LVS passes and the designer can continue. Reliable device fabrication at modern deep submicrometre 0. What is Antenna effect? The antenna effect. Cell-based methodology the general class that standard-cell belongs to makes it possible for one designer to focus on the high-level logical function aspect of digital-design.
What are stansdard Cell's? In semiconductor design. The LVS tool takes as an input a schematic diagram and the extracted view from a layout. Along with semiconductor manufacturing advances. A violation of such rules is called an antenna violation. Standard cell methodology is an example of design abstraction. Occasionally the phrase antenna effect is used this context but this is less common since there are many effects and the phrase does not make clear which is meant.
What is Clock distribution network? In a synchronous digital system. What are steps involved in Semiconductor device fabrication? This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order. The clock distribution network distributes the clock. See Electroplating Chemical-mechanical planarization CMP Wafer testing where the electrical performance is verified Wafer backgrinding to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.
What is Netlist? Netlists are connectivity information and provide nothing more than instances.
If they express much more than this. What is Clock Gating? Clock gating is one of the power-saving techniques used on many synchronous circuits including the Pentium 4 processor.
These connection points are called "ports" or "pins". Since this function is vital to the operation of a synchronous system. Most netlists either contain or refer to descriptions of the parts or devices used. Since the data signals are provided with a temporal reference by the clock signals. Clock signals are typically loaded with the greatest fanout. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance.
Clock signals are often regarded as simple control signals. Each time a part is used in a netlist. These observations have lead to a power saving technique called clock gating. An "instance" could be anything from a vacuum cleaner. Although asynchronous circuits by definition do not have a "clock". The clock distribution network often takes a significant fraction of the power consumed by a chip.
These definitions will usually list the connections that can be made to that kind of device. To save power. In the case of a vacuum cleaner. Logic synthesis with these technologies is becoming less important. Along with each instance. Each port has a name. SPICE is perhaps the most famous of instance-based netlists. There may or may not be any special attributes associated with the nets in a design.
This check results a database which has all the mismatching geometries in both the layouts. Previously only logic synthesis had to satisfy timing requirements. It is still required.
In this kind of description. LVS Layout versus schematic Check. XOR Checks. What Physical timing closure? Physical timing closure became more important with submicrometre technologies. Net-based netlists usually describe all the instances and their attributes. With present deep submicrometre technologies it is unthinkable to perform any of the design steps of placement. Instance based netlists usually provide a list of the instances used in a design. Most of the modifications are handled by EDA tools based on directives given by a designer.
Nets are the "wires" that connect things together in the circuit. This check is typically run after a metal spin. This allows for attributes to be associated with nets. Instances have "ports". The term is also sometimes used as a characteristic. When a physical representation of the circuit is available. Besides their names. What Physical verification? Physical verification of the design. EDIF is probably the most famous of the net-based netlists.
What is Different Logic family? If the connection to silicon does not exist. Antenna Check Antenna checks are used to limit the damage of the thin gate oxide during the manufacturing process due to charge accumulation on the interconnect layers metal. The antenna basically is a metal interconnect.
ERC Electrical rule check ERC Electrical rule check involves checking a design for all well and substrate areas for proper contacts and spacings thereby ensuring correct power and ground connections. What is Stuck-at fault?
A Stuck-at fault is a particular fault model used by fault simulators and Automatic test pattern generation ATPG tools to mimic a manufacturing defect within an integrated circuit.
Individual signals and pins are assumed to be stuck at Logical '1'. This rapid and destructive phenomenon is known as the antenna effect. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin..
ERC steps can also involve checks for unconnected inputs or shorted outputs. The Antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.
What is Different Types of IC packaging? IC are packaged in many types they are: During a latchup when one of the transistors is conducting. One of the advantages of this integration is low power dissipation for portability due to a reduction in the number of package pins and associated bond wire capacitance. What is Latchup?
A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component. In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal sent from the clock circuit arrives at different components at different times. This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely depending on the circuit's size arrive at different parts of the circuit at different times.
Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop.
If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.
If the destination flip-flop receives the clock tick earlier than the source flip- flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point. Clock skew can be minimized by proper routing of clock signal clock distribution tree or putting variable delay buffer so that all clock inputs arrive at the same time 3 What is slack? The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.
When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' call this Tact until the deadline call this Tdead. Negative slack implies that the 'actually happen' time is later than the 'deadline' time What causes it explain with waveform? How to overcome it? The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable.
When the enable is Low, the multiplexer feeds the output of the register back on itself.
When the enable is High, new data is fed to the flip-flop and the register changes its state 5 Given only two xor gates one must function as buffer and another as inverter? Tie one of xor gates input to 1 it will act as inverter. Tie one of xor gates input to 0 it will act as buffer. The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic.
For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. Difference between heap and stack? The Stack is more or less responsible for keeping track of what's executing in our code or what's been "called".
The Heap is more or less responsible for keeping track of our objects our data, well Think of the Stack as a series of boxes stacked one on top of the next. We keep track of what's going on in our application by stacking another box on top every time we call a method called a Frame. We can only use what's in the top box on the stack. When we're done with the top box the method is done executing we throw it away and proceed to use the stuff in the previous box on the top of the stack.
The Heap is similar except that its purpose is to hold information not keep track of execution most of the time so anything in our Heap can be accessed at any time. With the Heap, there are no constraints as to what can be accessed like in the stack.
The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet - we can grab what we need quickly. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it. A Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model.